1. Field of the Invention
Embodiments of the present invention relate to the fabrication of integrated circuits. More particularly, embodiments of the present invention relate to materials and processes for patterning and etching features in a semiconductor substrate.
2. Description of the Related Art
Integrated circuit geometries have dramatically decreased in size since such devices were first introduced several decades ago. Since then, integrated circuits have generally followed the two year/half-size rule (often called Moore's Law), which means that the number of devices on a chip doubles every two years. Today's fabrication facilities are routinely producing devices having sub-65 nm and even sub-45 nm feature sizes, and tomorrow's facilities soon will be producing devices having even smaller feature sizes.
The continued reduction in device geometries has generated a demand for methods of forming nanometer scale features that are separated by nanometer scale distances on semiconductor substrates. As the minimum feature size decreases, the semiconductor industry is facing the limitation of patterning sub-32 nm due to the limits of optical resolution being approached in current lithography processes. One method that has been developed to reduce the distance between features or devices on a substrate includes a double patterning of a hardmask layer that is used to transfer a pattern into the substrate.
One type of double patterning includes printing of a core pattern using conventional lithographical technology followed by subsequent deposition of a conformal spacer around the core feature. Following deposition of the spacer, various methods can be applied to achieve pattern density doubling that of the core.
In one version of double patterning, polysilicon is selected as the core patterning material. However, polysilicon has a high surface roughness which after deposition of subsequent film layers becomes decorated into bigger size defects. If neglected at the 32 nm node these defects can potentially cause lithographic and patterning defects which typically lead to killer defects such as broken patterns and bridged lines. This phenomenon is known as “Stack Defectivity” and is not limited to polysilicon substrates.
Therefore, there is a need for materials and processes for patterning and etching features in a semiconductor substrate that minimize the decoration effect, thereby significantly reducing stack defectivity.